Breaking the limits of x86

on YouTube ↗23m

" summary

Builds a cache-coherent fabric that maps DRAM from many motherboards into one global address space using a custom silicon 6-port chip and a kernel driver that extends APIC interrupt space into a 32-bit Linux IRQ space. Ships a global hardware timer, an ARM-based manager appliance for PXE/TFTP, and a JavaScript wiring tool for topology and cabling. Demonstrations include 34 TFLOPS from seven AMD Opteron nodes and a 5,000-core deployment achieving >10 TB/s STREAM bandwidth; firmware and drivers are open source on GitHub.

AI-written summary · about

" chapters (6)

1. 0:00Start
2. 2:18How is this done?
3. 3:23Scalable routing
4. 6:09Interrupt delivery teardown
5. 14:42Configuration
6. 21:29Questions and links

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