Xerxes: Extensive Exploration of Scalable Hardware Systems with CXL-Based Simulation...
summary
Simulation framework that models CXL 3 port-based routing and device-managed coherence and integrates DRAMSim3 for memory fidelity. Claims calibrated to real hardware with average error 4.3% (max <8%), can simulate 64 hosts in under 90 seconds using <200 MB, and shows LIFO victim policy cuts back-invalidations ~16% while an invalid-block length of two is optimal. Models PCIe 5/6 full-duplex links, lane contention, and header overhead, enabling concrete comparisons of topologies (tree vs spine-leaf) and measurable protocol tradeoffs; code is on GitHub.
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chapters (11)
- 0:00Introduction to Xerxes
- 1:02CXL 3 features and gap
- 2:03Existing simulator limits
- 3:06Xerxes design and architecture
- 4:09Device and interconnect layers
- 5:11Key components and coherence
- 6:56DRAMSim3 integration and clocking
- 7:16Hardware validation
- 8:19Design space insights
- 9:22Topology and coherence findings
- 10:04Physical layer summary
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