Evaluating Chiplet-based Large-Scale Interconnection Networks via Cycle-Accurate...
summary
A cycle-accurate packet-parallel simulator called CNSim implements an atomic-based hyper-threading model and packet-centric architecture to evaluate chiplet-scale shared-memory networks with heterogeneous router/link microarchitecture, hierarchical topologies, adaptive routing and real workload traces. It claims 11×~14× speedup versus existing cycle-accurate tools, achieves roughly 3× multithread scaling, shows latency deviation under 0.5% for heavy traffic, can simulate million-node (Tesla Dojo–scale) layouts and is open-sourced.
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chapters (10)
- 0:00Introduction
- 1:43Chiplet architectures essential
- 4:34Key differences from traditional
- 6:44Limitations of simulators
- 8:08Packet-centric simulator design
- 13:26Parallel simulation with threading
- 16:02Heterogeneous network links
- 17:51Simulation speed and accuracy
- 19:19Tesla Dojo evaluations
- 20:06Summary
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