Removing Obstacles before Breaking Through the Memory Wall: A Close Look at HBM...
summary
Study analyzes >460 million HBM error events from ~60,000 chips across 19 datacenters over two years and finds HBM-specific patterns: concentrate in 7th, 15th, 23rd, 31st columns, much higher error rates in lower HBM SIDs (thermal dissipation), column-related modes make up 29% vs row 5%, and two successive uncorrectable errors often occur within one hour with server power rising before failures. Implements Calchas, a hierarchical predictor combining spatial, temporal, and sensor features; tree models (GBDT) and an IF-style model reach ~60% precision/recall and identify ~65% of upcoming UEs.
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chapters (10)
- 0:00HBM memory challenges
- 2:32HBM structural limits and errors
- 4:01HBM error analysis method
- 6:11HBM error patterns
- 8:59Power/temp impact on HBM errors
- 11:10Traditional error prediction limits
- 12:37Hierarchical HBM predictor design
- 16:52Prediction timing and features
- 18:00Caucus predictor performance
- 19:24Findings and future directions
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