~/talk

HydraRPC: RPC in the CXL Era

Talkat USENIX ATC 2024 · 2024-07-10..07-12· [networking]
name:Teng Ma
links:none on file
name:Zheng Liu
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links:none on file
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links:none on file
name:Haoyu Li
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links:none on file
name:Dimin Niu
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name:Tao Ma
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slides:none on file

HydraRPC implements an RPC stack that mounts CXL-attached HDM, exposes 64-bit message-queue entries and preallocated data slots, and removes network round trips, memcpy and serialization by passing references into shared memory. It uses non-cachable CXL HDM with monitor/mwait notification to avoid busy polling, a user-space allocator and sliding-window flow control, and runs on real CXL 1.1 hardware. Measured latency is ~1.47 ms average with 99th-percentile 4x improvement and up to ≈100x speedups for 16B–2MB payloads versus RDMA/MRPC baselines.

AI-written summary · about

  1. 0:00HydraRPC and CXL intro
  2. 2:08CXL shared memory infrastructure
  3. 4:13Traditional RPC/RDMA limits
  4. 6:03HydraRPC architecture design
  5. 7:31Memory management in HydraRPC
  6. 9:00Request/response workflow
  7. 11:13Bypassing CPU cache
  8. 12:37Notification mechanisms
  9. 13:42Memory allocation & sliding window
  10. 15:30Performance results
  11. 17:24Summary & Q&A
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