Waverunner: An Elegant Approach to Hardware Acceleration of State Machine Replication
summary
Implements an FPGA SmartNIC (Xilinx U280) that moves only the common SMR data-replication path into hardware while leaving leader election and recovery to software, cutting PCIe crossings and freeing CPU cycles. Prototype uses 200 lines of C++ HLS and hits line-rate replication (≈100 Gbps, 26M pps) with 1.8 μs 99th-percentile latency on minimum packets; attached to memcached/Redis it reaches ~20M pps and cuts client tail latency from >40 μs to <12.5 μs, with automatic software fallback on failures.
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chapters (8)
- 0:00Start
- 3:15Distributed Protocol Performance Overheads
- 4:35Existing Hardware Acceleration Techniques
- 7:23Waverunner Hardware Design
- 9:44Experimental Setup
- 12:59End-to-End Application Throughput
- 14:07End-to-End Application Latency
- 15:07Conclusions
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