Linux-Ready-RV GC AndesCore with Architecture Extensions
summary
Andes ships a family of RISC-V cores (32- and 64-bit N25 series) with a configurable 5-stage pipeline, optional branch prediction, local cache with parity/ECC and an MMU option that enables Linux-ready 64-bit core boot via U-Boot and OpenSUSE ports. Integer multiply/MLA is one-cycle issue, FP divide/sqrt runs 15–29 cycles, small core targets ~1.0 GHz in a compact ~37K-gate profile while full-featured configs reach ~1.15 GHz. A custom extension tool generates RTL, compiler intrinsics, disassembler/debugger and simulation waveforms for domain-specific vector and DSP ops with fast desktop turnaround.
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chapters (7)
- 0:00Introduction to AndesCore
- 2:52RISC-V extensions overview
- 5:47AndesCore 25 series specs
- 8:44Custom extension toolchain
- 12:42Community collaboration
- 14:35Linux and open source support
- 15:19Conclusion and next steps
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