Use of RISC-V on Pixel Visual Core
summary
Evaluation integrates the PULP RI5CY RV32IMC core as a local microcontroller inside Pixel Visual Core to handle job scheduling and DMA control; choice favors systemverilog RTL, prior tapeouts, and a solderpad license. Integration uses Valtrix tooling including the Sting instruction generator for compliance tests, uncovers multiplier and load/store bugs that are patched, and shows good RTL quality but needs linting and a debug adapter conforming to the debug spec; next step measures runtime and power impact.
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chapters (9)
- 0:00Introduction and background
- 1:06Pixel Visual Core overview
- 2:10Open source microcontroller choice
- 3:53Core selection criteria
- 5:17Candidate cores comparison
- 7:21Decision to use RISC-V core
- 9:10Integration experience overview
- 12:19Recap and future steps
- 13:01Q&A session
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