Vector ISA
summary
RISC-V adds 32 vector registers V0–V31, a programmable VL register that limits active elements, and a V-config that selects register count and element width and V-config returns max VL for that configuration. Loads/stores support unit/strided/indexed access, there is scalar-in-vector support plus V0 low bit mask predication, splat/slide/merge ops, and FP16 as a vector datatype. Example loop adds a scalar to a 17,214-element array using 8-element VL chunks with no prologue/epilogue, handling the final 5-element tail.
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chapters (8)
- 0:00Introduction and spec status
- 1:48Why vector extensions matter
- 3:35RISC-V vector ISA basics
- 9:18Vector addition example
- 14:07Full vector instruction set
- 19:26Vectorizing a simple loop
- 32:46Loop assembly walkthrough
- 33:07Vector masking explained
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