Privileged ISA
summary
RISC-V privileged ISA defines hierarchical modes (user, supervisor, machine, debug) with 4k CSR address space divided as 1k per mode, mode-specific CSRs and dedicated CSR ops, and a minimal implementable CSR set (~12–16 registers). Virtual memory uses multi-level page tables (2–4 levels for RV32/RV64) producing 4 KiB, 2 MiB, or 1 GiB pages, with ASIDs and sfence instructions. Hardware offers up to 16 PMP regions (base/bounds, lockable), a physical memory attribute table, trap CSRs (mcause, mepc, mtval) and delegatable interrupts. Wait-for-interrupt and targeted interrupt delivery are supported.
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chapters (22)
- 0:00Intro
- 0:18Introduction to RISC-V Privileged Architecture
- 0:29Why a Privileged Architecture?
- 1:40RISC-V Privileged Architecture Layers
- 2:37Platform Profile Concept & Privileged Modes
- 3:33Some basic platform profiles
- 6:26RISC-V Privilege Modes
- 7:44Mode Specific Instructions
- 12:32CSR address space
- 15:02Memory Address Translation: Virtual Memory
- 17:38RISC-V Page Table Entries
- 20:31More control: Memory Fences
- 22:13RISC-V Virtual Memory Protections
- 24:15RISC-V Physical Memory Protection Unit
- 26:01Physical Memory Attributes
- 29:35Interrupts vs Exceptions
- 32:26Interrupt/Exception Handler Delegation
- 34:36Platform-Level Interrupt Overview
- 34:54RISC-V Interrupt Source Categories
- 35:49Software Interrupts
- 36:27Timer Interrupts
- 36:54External Interrupts
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