RISC-V Debugging: Custom ISA Extensions, Multicore, DTM Variants
summary
Lauterbach describes concrete support for RISC-V debugging using the Trace32 toolset including a hardware debug module and off-chip trace units, a claim of 40% market share for JTAG debuggers, and Linux kernel 4.15 Linux awareness for process, module and address tracking. Multicore features implement synchronous halt/reset/trigger across cores and asynchronous access to others. Two extension paths exist: hardwired tool integration or user plugins via the auxiliary serving processing units API, and notes fragmentation from custom IP and missing trace standard and DTM variants such as DTM mapping vs JTAG.
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chapters (6)
- 0:00Introduction
- 0:19What we do
- 2:14Risk 5 Debugging
- 4:46Multicore Debugging
- 7:35Custom ISA Extensions
- 10:32Standardization
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