Advanced Debug and Trace Tools for RISC-V Architectures
summary
Lauterbach demonstrates TRACE32 connected to a Microchip PolarFire SoC with an UltraSoC encoder and an FPGA AXI-to-PTI wrapper on GitHub that converts on‑chip buffers to a parallel/serial trace port; PowerTrace serial streams compressed data off‑chip, claiming real‑time compressed off‑chip trace up to 1T frames and gigabytes of storage for minutes–hours of recording. TRACE32 shows multicore control (E51 + U54×4), full Linux/MMU awareness, live patching, and a hands‑on Ultra96 setup (24 32‑bit soft cores) where attendees fix five bugs — fastest run 1 km in 41 s.
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chapters (8)
- 0:00Welcome and introduction
- 14:05Microchip’s RISC-V offerings
- 29:36Lauterbach tools for RISC-V
- 47:15Multi-core debugging demo
- 55:56Linux debugging demo
- 1:05:06Hands-on debugging session
- 1:48:28Bug fixing and performance demo
- 1:55:18Q&A and closing
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