UCAgent: An End-to-End Agent for Unit-Level Chip Verification
summary
UCAgent builds a Python-first verification flow that avoids generating SystemVerilog directly by wrapping RTL with picker and toffee, decomposes verification into a configurable 26-stage workflow where each stage has an automated checker, and attaches hierarchical labels via VCLM to keep specs, coverage models and tests aligned. Results show up to 98.5% code coverage and 100% functional coverage on UART/FPU/divider examples, reproduce real confirmed bugs, and are already in use by Xiangshan and several companies.
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chapters (7)
- 0:00Introduction to UCagent
- 8:08Background and motivation
- 13:09Challenges in LLM verification
- 19:53UCagent solution overview
- 24:56Experimental results
- 30:41Live demo walkthrough
- 47:33Q&A and closing
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