Hands-on TinyML Deployment on RISC-V: Building an Optimized Edge AI Pipeline - Corrected Audio
summary
Hands-on pipeline shows model-to-firmware flow using NN Pilot and Andes compute libraries to map TinyML (Visual Wake Word / MLPerf Tiny) onto the RISC‑V vector core X46 MPV via RVV-aware layout and pruning. Hardware‑aware pruning targets ~80% sparsity but enforces block alignment to vector length (128–2048), moving row-major to column-major so VFMACC replaces VFRSUM; result: ~1.5× speedup vs unpruned and nearly 2× vs standard pruning measured on a SystemC near‑cycle model. VM labs and autogenerated C runtimes are provided for reproducible runs.
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chapters (10)
- 0:00Introduction to workshop
- 1:53About Andes Technology
- 3:21X46 MPV hardware overview
- 5:10Andes AI toolchain flow
- 7:21Pruning in TinyML
- 12:50Hardware-aware pruning
- 13:12VM setup instructions
- 18:46Running the demo
- 23:50Performance comparison results
- 26:23Q&A and closing
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