Porting SIMD to RISC-V Vectors
summary
Covers RISC-V Vector (RVV) extensions, explaining RVV core concepts and design principles and comparing them with fixed vector-length SIMD approaches on other ISAs. Presents practical techniques for converting optimized C SIMD code from other architectures into RVV implementations, emphasizing differences introduced by RVV’s vector-length-agnostic (VLA) model.
AI-written summary · about
related talks
34mRISC V Vector Extension Proposal
13mUnleashing ML Processing Power Through RISC-V Vectors: Applications, Implementation and...
24mMoving to RISC-V Vector: A Practical Journey of AI Operator Optimization
36mPorting ML to RISC‑V: How Not to Lose Performance
13mKeynote: Taking RISC-V Intelligence Everywhere
11mSimulate, trace, and evaluate a RISC-V system leveraging very long vectors
45mThe Benefits of Building New AI Accelerators with RISC-V
17mExploring Static Code Generation and SIMD-Acceleration for Machine Learning on RISC-V