Building an AI Accelerator with High-Level Synthesis
summary
A RISC‑V co‑processor for wake‑word inference is implemented from C++ using High‑Level Synthesis (Catapult) and integrated via AXI into a Rocket Core SoC; quantization to 16‑bit (10 integer) reduces memory traffic and enables four 16‑bit accesses per 64‑bit beat. Loop unrolling and pipelining drop the dense layer from ~160 C‑steps to 16‑cycle latency, yielding software 26 µs versus 0.5 µs hardware for that layer; full hardware options trade area, power (~1.8 mW reported) and latency to meet the 50 ms window.
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chapters (9)
- 0:00Introduction and setup
- 2:42Wake word algorithm overview
- 7:46High-level synthesis workflow
- 15:21Software profiling and quantization
- 24:37Hands-on training steps
- 34:37Running the accelerator demo
- 41:50Power analysis and optimization
- 49:13Hardware-software integration
- 51:20Conclusion and next steps
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