The Benefits of Building New AI Accelerators with RISC-V
Talkat RISC-V Summit North America 2024 · on Tuesday, 2024-10-22· at 11:50· Grand Ballroom G (Level 1)·
summary
Argues that RISC-V reduces risk and speeds new accelerator work by letting teams plug in custom units while keeping common register-based interfaces so IP mixes. Gives concrete roles: RISC-V cores as software fallback for novel activations, sequencers or agent runtimes, and boot/security controllers. Reports that single‑core systolic designs (TPU v1 style) achieved strong reuse, many‑core designs need multicast-style dispatch, numerics are rapidly shifting to 4–8 bit formats, and memory and network bandwidth, not compute, remain the dominant bottlenecks.
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chapters (8)
- 0:00Introduction and context
- 2:23RISC-V value for AI
- 9:09Flexibility vs fragmentation
- 12:36Reuse vs customizability
- 19:23Core architecture choices
- 23:38Numerical representations
- 26:24Future AI models
- 30:09Call to action and Q&A
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