Lightning Talk: RISC-V and AI: How an Open-Standards ISA Underpins Portability f...
summary
RISC-V adds standardized AI extensions so vendors can drop in domain-specific accelerators while sharing the same OS and toolchain; Meta and Google are taping out RISC-V-based TPUs, stream Computing is shipping volume, and several vendors (Espiranto, Rivos, Softco) adopt cores. Two standards exist: integrated matrix extension (vector-based, no new microarchitectural state, ~2x–4x speedup) and attached matrix extension (separate accelerator tiles with large matrix registers for datacenter/HPC/edge). Goal is 95-98% shared infrastructure and avoiding vendor lock-in.
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