RISC-V: Changing the Way AI/ML Accelerators and Computing Infrastructure Are Built
Talkat RISC-V Summit North America 2024 · on Wednesday, 2024-10-23· at 13:55· Grand Ballroom H (Level 1)·
summary
Stream Computing describes an AME matrix extension built as tile/block matrix instructions with an 8+8 register design, elemental-wise ops and RVV-decoupled semantics, plus an open-source repo moving from v0.2 to v0.5. A mass-production STCP920 NPU card (FP16/INT8) ships thousands of units since 2022 and runs a full LLVM/AI-compiler stack with operator ports and an RVV/Matrix-enabled runtime. That stack powers a deployed large-model service—a 1,000P computing center project using 1,000 NPU cards (now ~150P live) and a 5,000-category knowledge graph for smart-community NLP.
AI-written summary · about
chapters (7)
- 0:00Introduction to AI and RISC-V
- 2:30Matrix extension development
- 8:17Implementation and evaluation
- 9:40Stream Computing products
- 10:36Software stack and compiler
- 14:48Smart community case study
- 17:19Talent cultivation and closing
related talks
13mKeynote: Taking RISC-V Intelligence Everywhere
22mAdvancing AI Computing With Optimized Matrix Multiplication Techniques With RISC-V CPU
19mAccelerating Edge AI with the Help of RISC-V
09mLightning Talk: RISC-V and AI: How an Open-Standards ISA Underpins Portability f...
30mRISC-V: Enabling Open Physical AI
09mA Tightly Coupled Light Weight Neural Network Processing Units With RISC V Core
40mAdvancing AI Application Development on RISC-V Platforms
17mRISC-V is Ready for Powering the Era of Intelligent General Computing
