Porting SLEEF to RISC-V

on YouTube ↗19m

" summary

SLEEF gets a complete RISC‑V port that implements single, double and quad precision math plus a DFT backend, with RVV targets for LMUL=1 and LMUL=2 and explicit handling of vector lengths. Build uses LLVM (clang) and relies on QEMU with zba/zbb/zbs enabled to emulate 128/256/512-bit and VL=5/12 testing. CI runs on QEMU on GitHub Actions and shows 62/62 tests pass, all via cross‑compile and vsetvl handling.

AI-written summary · about

" chapters (6)

1. 0:00Introduction to SLEEF
2. 1:47SLEEF architecture design
3. 4:41Porting challenges
4. 6:51RISC-V specific implementation
5. 11:05Build and test workflow
6. 14:02CI automation and conclusion

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