Keynote: Co-Designing Software and Hardware: Pillars of Advancing RISC-V for Application Success

on YouTube ↗15m

" summary

XuanTie outlines concrete work: four CPU IPs open-sourced on GitHub, delivered 2 GHz SoCs for development, and ports of Android and commercial Linux variants with SDKs and verification flows. Extension tooling uses a description language for custom ISA additions and accelerator tiles, yielding matrix 6x / vector 17x speedups in examples. Product rollouts include a high‑reliability R9 series and a c930 preview with a 15-stage out-of-order pipeline, aimed at storage, 5G and edge AI use cases.

AI-written summary · about

" chapters (7)

1. 0:00Software and hardware co-design
2. 4:32Multi-extension strategy
3. 4:59Customization and scalability
4. 6:53Accelerator-native architecture
5. 11:07Safety and reliability
6. 11:33Privacy and secure computing
7. 12:21Future applications and vision

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