Adaptable, Scalable and Predictable Computing with a Multi-threaded RISC-V Architectu...
summary
A new xcore RISC‑V design uses a 5‑stage pipeline with multiple register files to hold many hardware contexts so eight RISC‑V contexts per core time‑slice the single pipeline every cycle (at least five threads needed to saturate), and cores use distributed L1 memory (roughly 0.5 MB per core in current process). Synchronization uses a single‑cycle barrier and channels, DMA is implemented by threads, context save/restore costs tens–hundreds of microseconds, and a custom compact ISA (32k short encodings plus paired 32‑bit encodings, 12‑register subset) preserves code density so existing software can be ported.
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chapters (8)
- 0:00Introduction
- 0:20Background
- 1:01Why Multithreading
- 3:11Why Multicore
- 5:10The Threads
- 6:13The Barrier Mechanism
- 10:10The Heart Management
- 17:25Questions
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