Future is Sideways - Not Only Up and Right
summary
Andes unveils compact RISC-V cores tuned for MCU and automotive use: D23 is a 2–3 stage, highly configurable core with optional P (DSP) and B (bit) extensions, code-density and optional caches, claiming ~800 MHz at 28 nm and >4 CoreMark/MHz. A safety-certified N25FSE ships with a full safety manual and is described as fully asob certified for cabin radar, TDDI and automotive NCU; certification relies on the proprietary stack safe mechanism and reduced configuration set. Roadmap targets one safety core per year.
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chapters (9)
- 0:00Introduction and sponsor
- 0:45RISC-V plus CPUs
- 2:08Processor evolution
- 3:56Extra technologies
- 6:24Roadmap and new cores
- 7:27D23 entry-level processor
- 9:13Functional safety certification
- 12:46Future safety cores
- 13:07Q&A and closing
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