RISC-V SoC Coherency: Dealing with Unique RISC-V Coherency Issues

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Overview of RISC‑V nested virtualization with the Hypervisor (H) extension: architecture exposes HS mode plus VS/VM user modes, two‑stage guest→host translation becomes three‑stage for L2 via software shadow page tables, and H‑CSR and H‑instruction traps are handled lazily to avoid performance collapse. Virtual interrupt injection follows VSIP/VSI bits, page‑faults trigger nested exits and shadow TLB shootdowns, and a QEMU/Xvisor+KVM proof‑of‑concept shows huge pages speedup versus baseline.

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" chapters (10)

1. 0:00Introduction to talk
2. 0:42RISC-V hypervisor extension overview
3. 4:37Nested virtualization explained
4. 7:05Nested virtualization state switching
5. 9:54Lazy trapping of SRET instructions
6. 11:23Nested page fault handling
7. 13:34Nested recursion in RISC-V
8. 14:36Software status and demo
9. 16:00Live nested virtualization demo
10. 20:48Conclusion and Q&A