Demo: Introduction to RISC-V Verification with the Open Standard RVVI (RISC-V Verifi...

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" summary

RISC‑V processor verification consumes around 50% of SoC development cost, and RVVI proposes a concrete, open standard with three parts: RVVI Trace (a SystemVerilog tracer interface that captures async events), RVVI API (C/SystemVerilog/Python bindings supporting step‑in‑compare and register get/set), and virtual verification peripherals. Imperas ships the first commercial Imperas DV that implements the API, requires only a tracer to plug into existing testbenches, and publishes source on GitHub.

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" chapters (8)

1. 0:00Introduction to RVVI
2. 0:33RISC-V verification hurdles
3. 1:33The value of standards
4. 2:56RVVI architecture overview
5. 3:49Deep dive into RVVI components
6. 6:33Benefits of adopting RVVI
7. 7:25Practical applications
8. 9:30Summary and conclusion

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