RISC-V Open ISA’s Shock Wave of Processor Innovation Causing Seismic Shift
summary
Open RISC‑V implementations drive extensibility that raises verification from compliance checks into full system and security validation: designers report verification still consumes 60–70% of the project, emulation runs average 5–6 trillion cycles and FPGA prototyping soaks petacycles, and Breker debuts an SoC infrastructure app based on the Portable Stimulus standard. Teams use Imperas simulation, Cadence emulation/prototyping, formal reference models and Google’s open verification environment to catch microarchitectural, coherency and custom‑instruction bugs beyond basic compliance.
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chapters (20)
- 0:00Introduction
- 2:46Simon David Mann
- 8:08Mike Thompson
- 10:42Emerson
- 15:08Callen
- 16:56Frank
- 21:57Calista
- 31:43Security Verification
- 33:15Reference Model
- 34:08Compliance
- 35:16Compliance vs Verification
- 37:25Reference Specification
- 40:12Community
- 40:31Education
- 41:07Analogy
- 42:14SOC Comparison
- 43:21SSE Comparison
- 43:43Performance Analysis
- 44:18Test Synthesis
- 44:40Verification Issues
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