Code Size of RISC V versus ARM using the Embench™ 0 5 Benchmark Suite
summary
Comparison uses the Embench 0.5 benchmark suite and GCC to measure code size and speed across RISC‑V and ARM cores. Results show adding multiply/divide yields ~1.5–1.7× speedup and a 3–6% code‑size reduction; compressed instructions cut code size ~1.4–1.5× with negligible speed loss; M‑save/restore trims code size ~7% but costs ~10% performance; an embedded 16‑register RISC‑V is ~33% slower and ~7% larger than 32‑register variants. The study is reproducible and evolving.
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chapters (12)
- 0:00The problem with benchmarks
- 1:36Introducing Eembc
- 3:44Benchmark suite details
- 4:33Impact of compiler optimization
- 6:31Measuring speed and size
- 7:29Processor extension impact
- 9:15Summary of performance factors
- 10:33Compiler performance over time
- 11:31Architecture comparisons
- 12:53Register count analysis
- 15:08Future work and conclusions
- 17:17Q&A session
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