Compared Analysis of GCC Codegen for AArch64 and RISC-V
summary
Collected SPEC CPU2017 dynamic instruction count data on a Banana Pi F3–class config using fixed GCC builds and user‑mode QEMU with a hotspot plugin, comparing AArch64 (DSV2) vs RISC‑V (V). Key findings: a tight PARZ loop shows ~54–56% more dynamic instructions on RISC‑V because of missing scaled addressing mode (extra add then load), GCC generates extra moves instead of using the VFMA scalar form (patch cuts DIC ~4.7% but hardware timing only ~0.3%), memset calls cost ~21% of runtime on RISC‑V vs <1% on AArch64 (generic 46‑ins scalar fallbacks), and libm lacks target vector exps so RISC‑V sees ~32% instruction penalty.
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chapters (12)
- 0:00Introduction
- 0:15Motivation and context
- 1:40Dynamic instruction count metric
- 2:24Experimental setup
- 3:06Benchmark results overview
- 4:09ISA-related addressing issue
- 5:56Compiler vector instruction issue
- 7:41Library function performance gap
- 9:50AI-enhanced library optimization
- 10:55Future improvements
- 11:39Ongoing analysis updates
- 12:00Conclusion and Q&A
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