Recent Developments in Optimizing Compilers for RISC-V
summary
Uses Linux perf and PMU sampling to find hot, mispredicted branches and guide fixes at the binary level; example: a GCC global CSE loop replaced by a CTZ after preconditioning cuts a hotspot by ~0.25–0.5%, and a bitmap clear-bit rewrite removes a mispredicted store/load pair for ~1% gain. Shows unprofitable vectorization in x264 from heavy index/strided loads and poor cost models, and that the RVV zero-stride load idiom lowers instruction count ~5% but increases cycles ~5% on two microarchitectures. Notes VSETVLI speculation and VLEN=0 behaviors that cost ~1% and argues for ISA/profile guidance.
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chapters (9)
- 0:00Introduction and background
- 1:02Availability of RVV hardware
- 2:48Branch mispredictions in GCC
- 5:16Unprofitable vectorization cases
- 8:08Microarchitectural quirks in RVV
- 10:15Bad speculation in vector code
- 12:40Optimization guidance for RVA
- 13:42Index loads and zero-stride loads
- 14:48Q&A session
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