Optimizing Real-Time Application Requirements on ARC-V Processors Leveraging RISC-V Ex...
summary
Synopsys ARC-V implements custom RISC-V extensions that add a DMSI direct message signaling bus for deterministic interrupt delivery, a vectored table supporting 255 nested high-priority vectors, and hardware-managed stacked trap frames to cut prologue/epilogue context saves. Measured overhead is tens of instructions and only a few extra cycles even up to 8–16 cores, with area increase for nested vectors under 50% of a normalized IMIC and DMSI smaller, maintaining binary compatibility and no extra CSRs.
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chapters (12)
- 0:00Introduction and agenda
- 0:23Real-time in automotive systems
- 1:06Real-time determinism explained
- 2:33RISC-V scalability benefits
- 4:00AIA interrupt architecture overview
- 5:06Direct message signaling interrupts
- 6:12Nested vectored interrupts
- 7:18Trap stack pointer management
- 8:23Performance and area results
- 10:32Summary of real-time enhancements
- 13:19Future standardization plans
- 13:39Q&A session
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