OmniXtend: Open Coherent Memory Fabric for RISC-V

on YouTube ↗10m

" summary

Open coherent memory fabric that runs coherent over Ethernet and uses an FPGA fabric controller talking to a RISC‑V SoC; demo runs random memory accesses, memory pooling, and benchmarks. Adding 5 MB remote memory restores LLM inference from <1 token/s to 2.69 tokens/s (local baseline 2.74), showing bandwidth hides added latency. Protocol v1.0.3 supports cache coherence, retransmit and flow control; multi‑tenant sharing is currently separate regions per host, not fine‑grained isolation.

AI-written summary · about

" related talks

• 14mStrategies for CXL’s success in a world of proprietary Coherent...Allan J. Cantle · OpenPOWER Summit NA 2021
• 43mRISC-V CPU Project in Western DigitalZvonimir Z Bandić · ORConf 2018
• 17mRISC-V is Ready for Powering the Era of Intelligent General ComputingCharlie Su · RISC-V Summit North America 2025
• 24mKEYNOTE: RISC-V: Enabling a New Era of Open Data-Centric Computing ArchitecturesVivek Tyagi · RISC-V Workshop Chennai 2018
• 19mNuclei System Technology Releases UX1030H with Full Support for RVA23Dr. Peng Chen · RISC-V Summit North America 2025
• 01h 01mThe Genius of the RISC-V MicroprocessorErik Engheim · NDC TechTown 2021
• 17mThe Real Challenge for RISC-V Vector ProcessorsJohn Min · RISC-V Forum: Vector & Machine Learning 2021
• 13mKeynote: Accelerating Innovation with RISC-V: Past, Present and FutureManju Varma · RISC-V Summit 2022