Strategies for CXL’s success in a world of proprietary Coherent...
summary
Argues that adding small two‑port shared memory buffers and exposing local HBM/OMI channels as CXL-connectable resources lets CXL grow alongside proprietary coherent buses without consuming processor die area. Demonstrations: an A100-style HBM dual‑port yields 600% CXL bandwidth and 96 GB lendable; Power10 via LMI/OMI can present 128 CXL links and multiple terabytes; EPYC with OMI could fit 24 channels, ~1.5 TB/s and ~192 CXL lanes enabling ~6 TB lendable. Proposes chipletized controllers and shared memory buffer devices to keep low latency and preserve local bandwidth.
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chapters (11)
- 0:00Intro
- 0:25Reflect on recent Coherent Bus History
- 2:32HPC Architect's Challenges Today
- 3:04HPC Architect's Promised Land of Tomorrow
- 3:45CXL's Limited Scope for adoption While Proprietary Busses & local memory consume 10 resources
- 4:45What about Sharing Local/Near Memory As part of the CXL Shared Memory Pool
- 5:55Sharing Processors Local Memory over CXL Challenges
- 7:49Why not add CXL Ports thru a Shared Memory Buffer? Advantages
- 8:58CXL's opportunity via Shared Memory Allowing CXL to gain wider traction alongside Proprietary busses
- 12:21HPC Architect's Shared Memory Centric Solution
- 13:02Summary
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