Coriolis2 -- A FOSS RTL to GDSII toolchain

on YouTube ↗01h 04m

" summary

Coriolis2 converts HDL through Yosys into an ASIC netlist then performs placement, global and detailed routing, basic timing closure and GDSII output; the chain runs with Alliance, Flexlib and FreePDK/Sky130/TSMC180 support and uses a RTL to GDSII flow that shares data via a shared in-memory database and Python/C++ modules. Claims include a 1.3M-transistor LibreSOC layout ~28 mm² taped out to TSMC 180 nm (awaiting fab return), LVX netlist-vs-layout checking, and demonstrable place‑and‑route.

AI-written summary · about

" chapters (38)

1. 0:00Introduction to Coriolis
2. 1:05ASIC design flow basics
3. 7:12Roadblocks in ASIC design
4. 9:38Goals of Coriolis2
5. 13:59Target technologies
6. 16:06Symbolic vs real layout
7. 20:41History of Alliance and Coriolis
8. 23:31Steps to make an ASIC
9. 25:39Standard cell libraries
10. 27:07Placement in ASIC design
11. 28:52Metal layers and routing
12. 31:21Global and detailed routing
13. 33:08Electrical challenges in routing
14. 36:01Chip structure and automation
15. 37:24Tool integration challenges
16. 38:06Coriolis and Python integration
17. 39:30Design flow overview
18. 41:36LibreSoC chip details
19. 41:59Demo introduction
20. 43:24Design script explanation
21. 44:06Clock tree placement
22. 45:10Cell placement and legalization
23. 46:14Filler cells and power lines
24. 46:57Fly lines and net selection
25. 47:41Global routing process
26. 48:23Debugging routing density
27. 49:50Finalizing the design
28. 50:53Netlist verification
29. 51:37Technology support progress
30. 52:19Q&A session begins
31. 52:40SPICE simulation capabilities
32. 54:05Reverse engineering cells
33. 56:31Handling NDAs in technologies
34. 57:11Collaboration on TSMC 180nm
35. 59:19Advanced routing algorithms
36. 1:00:46Progressive refinement in routing
37. 1:01:51RF and analog design support
38. 1:03:19Closing remarks

" related talks

• 40mKeynote: Open Source FPGA ToolingMatt Venn, Claire Wolf, Slyvain "tnt" Munaut · GNU Radio Conference 2021
• 18mOpen source chip design: for fun and for profitAndreas Olofsson · ORConf 2025
• 24mTeaching Open Silicon Design in a Quarter: Using Cloud-based Open Agile EDA PlatformYuchi Miao · Latch-Up 2025
• 01h 00mOpenROAD: The journey so far and roadmapAndrew Kahng · ORConf 2023
• 44mASICone, from Verilog to GDSII with open source toolsLuis E. Rueda G. · ORConf 2019
• 24mBootstrapping a real working design flowTim Edwards · Week of Open Source Hardware 2019
• 21mGDSFactory: Open-Source EDA for Photonics, Quantum, MEMS, and RF Chip DesignRishabh Iyer · Latch-Up 2026
• 10mKeynote: The Open Source Hardware RoadmapZvonimir Z Bandić · RISC-V Global Forum 2020