Testing Framework to port and optimize SIMD library to Systems
summary
Framework ports Intel x86 SIMD intrinsics to OpenPOWER ISA by running the same tests on two machines connected over the network and asserting identical results. It implements a network module in Python, a C extension for Python testing module, a shared random m256d generator to feed identical inputs, and comparison of outputs plus latency and throughput measurements. Tests run on real hardware or QEMU controlled via GDB/MI to read registers. The project is open source and aims for bit‑identical correctness.
AI-written summary · about
chapters (5)
- 0:00Introduction to SIMD porting problem
- 2:53Need for testing framework
- 7:14Testing framework design
- 9:03Community collaboration plans
- 13:12Q&A and contact details
related talks
11mBuilding a Test for Diverse Fleet of Platforms, How Hard That Could Be?
24mRISC V Processor Verification based on Open source Framework
14mMicroprobe: An Open Source Microbenchmark Generator Ported To The RISC V ISA
16mSoftware Development for 64-Bit RISC-V Processor Verification
25mRISC-V System-level Certification from Verification Foundations
18mTesting Intel TDX functionality with new set of self tests
23mOpen Source Verification Platform for RISC V Processors
19mrtesbench: A Multi-core Benchmark Framework for Real-Time Embedded Systems
