Microprobe: An Open Source Microbenchmark Generator Ported To The RISC V ISA
summary
Microprobe is an IBM microbenchmark generator ported to the RISC‑V ISA and intended as open source (pending review). It consumes YAML target definitions and Python generation policies, parses rv8 / riscv-meta to build an ISA back end, and emits C, assembly or binaries. Example workflow generates loops of 100 instructions, sweeps dependency distance, and runs on Rocket chip emulator or FPGA to extract latencies/throughputs — e.g. add = latency 1 throughput 1, FP pipelines show linear throughput, mul/div are multi‑cycle.
AI-written summary · about
chapters (8)
- 0:00Introduction
- 0:50Why make micro benchmarks
- 2:20What is Microprobe
- 2:58User Stories
- 5:49Risk V
- 9:41Example
- 10:44Code
- 13:19Summary
related talks
23mOpen Source Verification Platform for RISC V Processors
24mRISC V Processor Verification based on Open source Framework
16mAutomated Certification and Benchmarking for RISC-V Architectures
17mRecent Developments in Optimizing Compilers for RISC-V
22mRISC-V Perf-Model: An Open Source Cycle Accurate Performance Mo...
10mRISC-V Instruction Set Explorer (RISE)
16mTowards Open-Source and Automatic Performance Characterization Hardware
36mAccelerate RISC-V Instruction Set Simulation by Tiered JIT Compilation