RISC V Hypervisor Extensions
summary
Proposal adds a RISC‑V hypervisor extension that virtualizes supervisor mode by introducing HS/VS/VU modes, exposes background CSRs to hold guest state without heavy copies, and uses two‑level translation (guest→guest‑phys then hypervisor page tables→machine) with identical page table formats. Design targets both bare‑metal and KVM‑style hybrid hypervisors, supports recursive guests with shadow page tables, and includes machine‑mode traps for sret/sfence to ease emulation. Spec is in the ISA repo; no hardware or full software implementations exist yet, Spike/QEMU ports planned.
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chapters (11)
- 0:00Intro
- 0:42Purpose & Goals
- 2:07RISC-V Privilege Modes
- 2:58Privilege Modes with Hypervisor Ext.
- 4:36What Needs to be Virtualized?
- 4:53Virtualizing Supervisor Arch. State
- 7:35Virtualizing Memory
- 8:40Virtualizing 1/0 and Interrupts - Software & Timer interrupts use SBI (= trivial)
- 10:27Recursive Virtualization • Recursive virtualization supported with additional HS- level software support
- 10:56Emulating the Hypervisor Extension
- 11:54Implementation Status
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