BOOM v2: An Open Source Out Of Order RISC V Core
summary
An open‑source out‑of‑order RISC‑V core written in ~16k lines of Chisel is generated inside the Rocket Chip ecosystem, taped out in TSMC 28nm after a two‑person, four‑month push using a commercial memory compiler and P&R flow. Key changes: add a pipeline stage and move hashing, replace a 30‑entry fully associative BTB with an SRAM 200‑entry partially tagged BTB, split the issue window and register files and hand‑blackbox a multiport RF with tri‑state bitcells. Result: silicon returned, ~25% shorter clock period but ~20% workload loss from an extra load‑use cycle; tradeoffs are identified and fixable.
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chapters (7)
- 0:00Introduction to BOOM
- 3:12Why BOOM v2 now
- 7:29Critical path fixes
- 10:58Register file redesign
- 13:25BOOM v2 results
- 14:52Agile hardware development
- 17:18Future directions
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