GRVI Phalanx Update: Plowing The Cloud With Thousands Of RISC V Chickens

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" summary

A reconfigurable overlay of simple RISC-V cores and a hoplite NoC runs as an FPGA accelerator fabric and compiles C++/GCC kernels into many-core jobs without full bitstream flow. Implementations run on Xilinx UltraScale+ (AWS F1), with a 1,680‑core prototype using 26 MB scratchpad SRAM at ~250 MHz and a plan for ~10,000 cores per large instance (1680 cores, 26 MB SRAM, 250 MHz). Measured fabrics show massive on-chip bandwidth and low power per core, and the system already uses AXI bridges, message/RDMA gateways, SDAccel/OpenCL tooling and bare‑metal C++ for validation (2.5 TB/s memory bandwidth, ~1 Tb/s NoC, 25 mW/core).

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" chapters (11)

1. 0:00Introduction to GRVI Phalanx
2. 1:04Accelerator kit overview
3. 2:09GRVI processor design
4. 3:33Cluster architecture
5. 4:15Hoplite NoC details
6. 5:17Amazon EC2 F1 deployment
7. 6:241680-core FPGA design
8. 7:29Software developer kit
9. 8:54F1 system layout
10. 10:19OpenCL programming model
11. 11:43Summary and future

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