RISC V State Of The Union

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Overview of current RISC-V status and near-term roadmap: the base ISA is base frozen since 2014 and privileged ABI stabilized at 1.10; Linux upstream lands in 4.15 and GCC 7.1 is GCC 7.1 mainline with binutils support. Memory model work converges on a weak memory model plus optional TSO and formal axiomatic/operational specs with litmus checkers. Vector design adds matrices for ML/DSP, a hypervisor spec targets KVM, a J-extension group tackles JIT/GC needs, and there is still no Unix-capable RISC-V SoC commercially available.

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" chapters (22)

1. 0:00Intro
2. 0:44What is RISC-V?
3. 2:02What's Different about RISC-V?
4. 3:45RISC-V Timeline
5. 8:27Government Adoption
6. 9:28Startups
7. 10:16Commercial Ecosystem Providers
8. 10:28RISC-V in Academic Research
9. 13:05RISC-V: Completing the Innovation Cycle
10. 15:23Upcoming Events
11. 20:22Expanded naming of instruction sets
12. 22:05Profiles for Software Compatibility
13. 23:31Memory Model
14. 26:23ABI and Compilers
15. 28:19Other OS Ports
16. 29:40Vector Extensions
17. 30:39Security
18. 31:31Interrupts
19. 33:38J Extension
20. 34:16RISC-V Technical Priorities for 2018
21. 35:13Summary
22. 36:09Questions?