Rocket Engines: Low Effort Design Reuse In RISC V Implementations
summary
A new three‑stage core called Bottlerocket reuses RocketChip subcomponents to produce an RV32IMC microcontroller-style CPU with privilege 1.10, SiFive debug, JTAG transport, RVFI trace and a constant‑time multiplier/divider. A tiny 10–20 line Chisel top generator emits either a full tile or the big three blocks; only 14.5% reuse of RocketChip lines yields a completely different microarchitecture, while the CSR implementation is twice as large as the new core’s code. Integration targets weeks, not months, and RVFI is used for debugging and formal integration.
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chapters (9)
- 0:00Introduction to Rocket Chip
- 0:38The value of design reuse
- 1:22Why custom cores emerge
- 2:34Pitfalls and validation
- 3:37Modular architecture
- 5:01Key reusable components
- 5:59Introducing Bottlerocket
- 7:14Implementation and features
- 8:36Summary and future outlook
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