The PULP Cores: A Set Of Open Source Ultra Low Power RISC V Cores For Internet Of Things...
summary
An open source family of RISC‑V cores targets ultra low power IoT workloads with near‑threshold operation and on‑chip parallelism, multiple taped‑out silicon instances and full tooling. Claimed designs include a DSP‑optimized core at 40–70k gates, a minimal control core as micro RISC‑V <12k gates, a 64‑bit out‑of‑order core aiming for >1 GHz on 22 nm GF, and an 8‑core cluster with shared FPU plus DMA. Releases on GitHub include RTL, an instruction set simulator, profiling tools, and a genetic program generator used for coverage‑driven verification.
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chapters (11)
- 0:00Introduction to PULP cores
- 1:06Overview of PULP core variants
- 2:14Deep dive into RI5CY core
- 3:41PULP extensions and optimizations
- 4:25Introduction to Zero-riscy core
- 5:28Micro-riscy and 64-bit cores
- 6:34PULP software ecosystem
- 7:38Verification and testing methods
- 8:43Industry and academic adoption
- 9:28PULP platform architecture
- 10:31Future releases and tape-out
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