RISC5: Improving Support For RISC-V In Gem5

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" summary

Adds full RV64I + IMAFDC support to gem5, implementing integer, multiply, atomic, floating-point and compressed instruction handling and a decoder that copes with 2- and 4-byte alignment. Current build runs single-threaded with system-call emulation, saves/restores states to warm caches, and is verified against Spike and Rocket Ship for FP exceptions and correctness. Missing: privileged-mode support and pthread/m5threads multithreading; full-system boot image and one FP rounding mode remain to implement.

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" chapters (8)

1. 0:00Introduction to RISC5 in Gem5
2. 2:47Integer and multiply instructions
3. 4:10Atomic instructions implementation
4. 5:37Floating-point extensions
5. 6:48Compressed extension challenges
6. 7:56Demo of power and temperature simulation
7. 9:03Roadmap for full RISC5 support
8. 10:10Summary and Q&A

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