Customization Of A RISC V Processor To Achieve DSP Performance Gain

on YouTube ↗09m

" summary

Uses Codasip Studio and a CodAL high-level description to add ISA extensions, run the profiler, and auto-generate SDK, RTL and UVM. Tests compare four configs: integer-only, +mul/div, +parallel multiplier, and custom DSP instructions; implementation takes three days. Results show reduced clock cycles and smaller code size at modest area increase, with the final config delivering 56.24× performance gain on an IoT audio workload after adding DSP ops and a parallel multiplier.

AI-written summary · about

" chapters (8)

1. 0:00Intro
2. 0:44CODASIP STUDIO
3. 1:58STEP: BK SELECTION
4. 2:49STEP: ISA CONFIGURATION
5. 4:07STEP: NEW INSTRUCTIONS
6. 4:43STEP: AUTOMATED GENERATION
7. 5:26THE MICROSEMI USE CASE: AUDIO PROCESSING SOLUTION FOR IOT
8. 5:52THE MICROSEMI USE CASE: STEPS 1. STEP: Berkelium core selection

" related talks

• 01h 10mWhy RISC-V Through ISA Customization DemonstrationKeith Graham · RISC-V Summit North America 2023
• 11mScale4Edge RISC-V EcosystemAndreas Mauderer · RISC-V Summit Europe 2024
• 11mDriving SoC Innovation with Synopsys RISC-V SolutionsRich Collins · RISC-V Summit Europe 2024
• 14mKeynote: Solving the Conundrum of Custom InstructionsSimon Davidmann · RISC-V Summit North America 2023
• 17mDemo: RISC-V Models for Verification, Software Development and Architectural Explor...Larry Lapides · RISC-V Summit 2022
• 17mUnlocking 15% More Performance: A Case Study in LLVM Optimization for RISC-VMikhail R. Gadelha · RISC-V Summit North America 2025
• 20mRISC V Software State of the UnionRandy Allen · RISC-V Summit 2019
• 01h 25mRISC V Bit Manipulation ISA Extension Spec, Hardware, SoftwareKen Dockser · RISC-V Summit 2019