The Case For Expanding The 16 GPR Standard Beyond RV32E
summary
Argues for making the 16-GPR option orthogonal to other RISC-V extensions and shows a concrete implementation: modified GCC and G Lipsy toolchains plus the gem5 simulator to evaluate a reduced ISA called V64R (architected registers x0–x15 and f0–f15). Benchmarks (CoreMark, Dhrystone, Whetstone, reduced SPEC) show ~6% static code size increase, ~0.5% more dynamic instructions on average, OoO execution time improves ~1% for many integer workloads, while floating-point suffers ~4–5% slowdown and one FP pathological case fails badly.
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chapters (7)
- 0:00Introduction
- 3:00Market Demand
- 4:29Methodology
- 6:58Benchmark Results
- 9:26Limited Designs
- 10:28Benefits
- 11:18Conclusion
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