A RISC V Based Linear Algebra Accelerator For SoC Designs
summary
Describes the LA core: a RISC-V extension with 68-instruction RISC-V extension that adds a dual-precision systolic LA exec unit, four configurable LA mem units, a 64 KB scratchpad and a 64 KB LA L1 cache. Implements sparse-matrix hardware and gather/scatter in the LA mem units and exposes a 3-category API (config, data-move, execute). Evaluated in gem5 and Spike with a GCC toolchain on HPCC benchmarks, open-sourced on GitHub, and reports 3.4x vs x86; 10x vs RISC-V; 12x vs GPU while estimating area ~2.5× a scalar RISC-V.
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chapters (10)
- 0:00Lightweight Linear Algebra in HPC
- 3:13LACore Architecture: Overview
- 4:33LACore Architecture: LAExecUnit
- 5:23LACore Architecture: LAMemUnit
- 6:26LACore Architecture: LACfg, LACache, Scratchpad
- 7:58LACore Instruction Set and LACoreAPI
- 10:27HPCC Evaluation in gems
- 12:14LACore is Freely Available
- 12:49LACore simulators and benchmarks
- 14:14Conclusions and Future Work
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