Samuel Steffl
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| title | conference | date |
|---|---|---|
| Poster / Demo Previews | 7th RISC-V Workshop 2017 | 2017-11-28 |
Poster session collates runnable claims and working demos: an open-source framework that formally verifies RISC‑V cores and emits monitor code used on real… | ||
| A RISC V Based Linear Algebra Accelerator For SoC Designs | 7th RISC-V Workshop 2017 | 2017-11-28 |
Describes the LA core: a RISC-V extension with 68-instruction RISC-V extension that adds a dual-precision systolic LA exec unit, four configurable LA mem… | ||
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