Porting The ThreadX RTOS To RISC V

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" summary

Express Logic ports ThreadX to RISC-V, implements port to RISC V and verifies it with Spike simulation then on a Microsemi SmartFusion development board, running an 8-thread stress test (timers, queues, semaphores, mutexes) overnight. ThreadX retains preemption-threshold scheduling, real-time event trace into a circular buffer and memory-protected modules, advertises a minimal ROM footprint around 2 KB, SIL-4/Class C/D safety certifications, and publishes service timings in four modes; commercial, royalty-free licenses with full source aim for release before year end.

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" chapters (11)

1. 0:00Intro
2. 0:17Background
3. 1:19ThreadX Overview
4. 3:19Preemption-Threshold™ Scheduling
5. 4:28ThreadX Event Trace
6. 5:27ThreadX Application Modules
7. 6:49Testing The Port
8. 8:05Final Test
9. 9:05ThreadX Footprint
10. 10:13ThreadX Service Times
11. 11:36Current Status and Resources

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