Scale4Edge RISC-V Ecosystem

on YouTube ↗11m

" summary

Customized RISC-V chip integrates processor core (tgcc from minus) with CDSL-defined custom instructions—signed saturation, packed dot 8‑bit and zero‑overhead loops—on a GF 22 FDX test chip; integration and compiler/virtual-prototype changes take about one to two weeks and software bring-up two to three days, overall around three weeks. Measured outcome is 15% area overhead, 2x performance and ~30% power savings, and a live demo reports 100% siren detection using a PCM stream.

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" chapters (7)

1. 0:00Introduction and project overview
2. 1:07Custom RISC-V chip for siren detection
3. 2:10Development flow and custom extensions
4. 3:34Chip integration and software bring-up
5. 5:00Live demonstration of the chip
6. 7:30Key results and summary
7. 7:51Q&A session

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