UnityChip Verification: Open-Source RISC-V Verification at BOSC

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" summary

Verification cost dominates chip schedules: only 24% of ASICs hit first silicon in 2022 and projects spend 50–60% of time on verification, with logical failures above 50%. UnityChip builds an open verification flow around an autogen Picker API that exposes RTL as high‑level calls (step, clock, reset) and runs with Verilator today (VCS, Quest planned). It also implements peer transactions that pack/unpack bytestreams to bridge UVM and Python reference models. Xiangshan RISC‑V CPU is used as a case study and the approach demonstrably reduces RTL reference modeling effort and preserves RTL behavior.

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" chapters (9)

1. 0:00Introduction
2. 1:09Verification background
3. 2:33Traditional verification limits
4. 3:16UnityChip verification intro
5. 4:00Picker RTL API solution
6. 5:07Python testbench example
7. 6:12UVM Python integration
8. 9:29Workflow summary
9. 9:50Q&A session

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