RISC-V enabled, low-power CNN classification in Edge devices

on YouTube ↗11m

" summary

A pulse-coherent radar produces streaming matrices that feed two small CNNs (distance and phase/velocity) running on a programmable near-memory computing co‑processor attached to a RISC‑V MCU; an FPGA demo reproduces a planned 22 nm die and shows a 98% CPU offload versus doing inference on the core, claiming large power savings. JTAG is used for demo connectivity today (SPI/real sensor integration and final power numbers pending).

AI-written summary · about

" chapters (6)

1. 0:00Introduction and demo overview
2. 2:07Application and radar sensor
3. 3:51System architecture and co-processor
4. 5:45CPU offload and power saving
5. 7:11Dual neural networks explanation
6. 8:19Collaboration and Q&A invitation

" related talks

• 17mNext-Generation Edge AI with RISC-V Vector Cores for Vision ApplicationsFlorian Zaruba · RISC-V Summit North America 2025
• 13mAdding A Binarized CNN Accelerator To RISC V For Person DetectionGuy Lemieux · 7th RISC-V Workshop 2017
• 13mKeynote: Taking RISC-V Intelligence EverywhereCharlie Su · RISC-V Summit North America 2023
• 19mAccelerating Edge AI with the Help of RISC-VFlorian Zaruba · RISC-V Summit North America 2023
• 06mEmbedded Executive LIVERich Nass, Steve Brightfield · embedded world North America 2026
• 09mA Tightly Coupled Light Weight Neural Network Processing Units With RISC V CoreLei Zhang · 7th RISC-V Workshop 2017
• 14mKeynote: RISC-V Opportunities at the Edge of AIMakeljana Shkurti, Ed Doran · RISC-V Summit North America 2025
• 12mCustomizing RISC-V Cores to Accelerate Neural NetworksJon Taylor · embedded world 2022